Due to the rise in popularity of ultra-low power applications, the reduction in power dissipation has received more attention. Due to its lower power dissipation, Sub-threshold Adiabatic Logic (SAL) is a technology that can be very beneficial. This paper presents four sets proposed subtractors that have been implemented in 90nm technology utilizing CADENCE Virtuoso software and both the SAL approach and conventional CMOS logic. The proposed subtractors aim to attain lower power dissipation and count transistors while additionally considering design accuracy into account. The circuit parameters have been analyzed, and these circuits are further compared to conventional subtractors. The proposed approximate subtractor APSUB1 is 51% more efficient than the least power dissipated circuit of the recent existing circuit which is APSC6. When comparing the power dissipation using CMOS and SAL technique, there has been a power reduction of 17% for APSUB1 circuit when implemented by SAL. By employing the SAL technique, the proposed subtractors have an efficient improvement in the circuit aspects and a further reduction in the power and area of the design. Eventually useful in agricultural Control engines, because of its low-power and energy-efficient features.